Description
NED82C55 D8255AC-2 DIP-40 D82C55-2 Programmable Parallel I/O Interface IC Chip DIP-40 D8255AC-2
Product Description
(1) A parallel input/output LSI chip, multi-functional I/O device can be used as an interface between the CPU bus and the periphery. (2) There are 24 programmable I/O ports, even if the 3 groups of 8-bit I/O ports are PA, PB and PC ports. They can be divided into two groups of 12-bit I/O ports. Group A includes port A and port C (high 4 bits, PC4~PC7), group B includes port B and port C (low 4 bits, PC0~PC3). Group A can be set as basic I/O port, flash control (STROBE) I/O flash control, two-way I/O 3 modes; Group B can only be set to basic I/O or flash control I/O, and these operations The mode is completely determined by the control word of the control register.
Specification
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RESET
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Reset input line. When the input terminal is at high level, all internal registers (including control registers) are cleared, and all I/O ports are set to input mode.
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CS
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Chip selection signal line. When this input pin is low, that is, when /CS=0, it means that the chip is selected and allows 8255 to communicate with the CPU; when /CS=1, 8255 cannot communicate with the CPU.
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RD
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Read signal line. When this input pin is low, that is, /RD=0 and /CS=0, the 8255 is allowed to send data or status information to the CPU through the data bus, that is, the CPU reads information or data from the 8255 .
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WR
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Write signal. When this input pin is low, that is, when /WR=0 and /CS=0, the CPU is allowed to write data or control word into 8255.
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D0~D7
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Three-state bidirectional data bus, the channel of 8255 and CPU data transmission. When the CPU executes input and output instructions, it realizes 8-bit data read/write operation, and the control word and status information are also transmitted through the data bus.
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PAO~PA7
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Port A input and output lines, an 8-bit data output latch/buffer, and an 8-bit data input latch.
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PB0~PB7
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Port B input and output lines, an 8-bit I/O latch, and an 8-bit input and output buffer.
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PC0~PC7
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Port C input and output lines, an 8-bit data output latch/buffer, and an 8-bit data input buffer. Port C can be divided into two 4-bit ports by working mode settings. Each 4-bit port contains a 4-bit latch, which is used in conjunction with port A and port B, and can be used as control signal output or status signal Enter the port.
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A0, A1
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The address selection line is used to select the PA port, PB port, PC port and control register of 8255.
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When A0=0, A1=0, PA port is selected; When A0=0, A1=1, PB port is selected; When A0=1, A1=0, the PC port is selected;
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